We model a 200-cycle latency to memory at the high frequency (2.1GHz for a single processor). The memory latency (in cycles) decreases when we use lower frequencies for the 2-core and 4-core systems. For the 2-core system running at 1.4GHz, memory latency decreases to 130 cycles as the cycle time is longer. For the 4-core processor running at 825MHz, memory latency becomes 80 cycles. We support a maximum of 32 outstanding misses to memory. We implement four memory controllers per chip, each with a 6GB/sec bandwidth to memory, for a total of 24GB/sec memory bandwidth. This bandwidth is shared between all cores in the system, so the bandwidth per core is higher for our single-core (24GB/sec/core) and 2-core (12 GB/sec/core) compared to our 4-core system (6GB/sec/core).