One aspect that can be investigated in detail is the con-nection between theoretical estimations and practical evalua-tion. The impact of an additional processor core as well as
the Cordic coprocessor on the speedup are analyzed. When
caching effects are studied, the cache size and caching strategy
can be varied and possible changes discussed. The results of a
different associativity level or the change from FIFO to LFU
becomes comparable to models previously devised. Also the
on-chip communication by means of the shared registers and
memory communication can be set in relation to one another.