Memory Observe (DMO) using Macrotest. DMO reduces test
time by enabling fast bit-mapping required for array repair. The
Transition Test technique is used for speed testing of targeted
critical paths. SERDES designs incorporate external, internal,
and pad loopback capabilities to enable their testing. Architecture
design enables use of 8 SPCs and/or L2 cache banks.
This has proved to be a valuable feature for Niagara2 because
it has shortened our debug cycle by making partially functional
die usable. It will also provide an additional advantage of
increasing overall yield by enabling partial core products.