All the IMs are connected to a central controller. Each IM
sends a message to the central controller to notify the cell
arrivals to its VOMQs every time slot. The controller maintains
an n n counter matrix to track the backlogs of the
VOMQs. A scheduler executes the scheduling algorithm
and sends the results to the IMs and CMs every time slot.
The purpose of the counter matrix in the controller is to
effectively cope with the propagation delay between the
IMs and the scheduler. So every time slot, the scheduling
Fig. 2. The three-stage shared-memory switch architecture.
XIA ET AL.: A PRACTICAL LARGE-CAPACITY THREE-STAGE BUFFERED CLOS-NETWORK SWITCH ARCHITECTURE 319
can be executed by the controller itself without waiting for
the requests from the IMs. The communication overhead of
this notification scheme will be discussed in Section 6