The watchdog module generates an output pulse, 512 oscillator-clocks (OSCCLK) wide whenever the 8-
bit watchdog up counter has reached its maximum value. To prevent this, the user can either disable the
counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register
which resets the watchdog counter. Figure 31 shows the various functional blocks within the watchdog
module.