2.2. STM32 F1
controlled by the core with load and store instructions that access memorymapped registers. The peripherals can “interrupt” the core to request attention through peripheral specific interrupt requests routed through the NVIC. Finally, data transfers between peripherals and memory can be automated using DMA. In Chapter 4 we discuss basic peripheral configuration, in Chapter 11 we show how interrupts can be used to build effective software, and in Chapter 12 we show how to use DMA to improve performance and allow processing to proceed in parallel with data transfer.
Throughout this book we utilize the ST Standard Peripheral Library for the STM32 F10xx processors. It is helpful to understand the layout of this software library. Figure 2.7 provides a simplified view of the directory structure. The library consists of two major sub-directories – STM32F10x_StdPeriph_Driver and CMSIS. CMSIS stands for “Cortex Micro-controller Software Interface Standard” and provides the common low-level software required for all ARM Cortex parts. For example, the core_cm3.* files provide access to the interrupt controller, the system tick timer, and the debug and trace modules. The STM32F10x_StdPeriph_Driver directory provides roughly one module (23 in all) for each of the peripherals available in the STM32 F10x family. In the figure, I have included modules for general purpose I/O (GPIO), I2C, SPI, and serial IO (USART). Throughout this book I will introduce the modules as necessary.
There are additional directories distributed with the firmware libraries that provide sample code which are not illustrated. The supplied figure provides the paths to all of the key components required to build the tutorials in this book.
The STM32 F1 has a sophisticated clock system. There are two primary external sources of timing – HSE and LSE. The HSE signal is derived from an 8MHz crystal or other resonator, and the LSE signal is derived from a 32.768 kHz crystal. Internally, the HSE is multiplied in frequency through the use of a PLL; the output of this, SYSCLK is used to derive (by division) various onchip time sources include clocks for the ABP1 and APB2 peripherals as well as for the various programmable timers. The LSE is used to manage a low-power real-time clock. The STM32F100 micro-controllers can support a maximum SYSCLK frequency of 24MHz while the other STM32 F1xx micro-controllers support a SYSCLK frequency of 72MHz. Fortunately, most of the code required to manage these clocks is provided in the standard peripheral library module (system_stm32f10x.[ch]) which provides an initialization function – SystemInit(void) to be called at startup. This module also exports a variable SystenCoreClock which contains the SYSCLK frequency; this simplifies
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