inter- and intra-chip communication [2], [3] resulting to powerful
machines with up to 40 Gb/s line-rate capabilities and
Tb/s throughput [4]. However, given that HPCS are already
entering the Peta-Flops regime [3], a new set of challenges
are expected to strain the data center networking infrastructure
as the increase of the processor throughput is exceeding the
improvement rate of memory speeds. From a design perspective,
a balanced system requires equal improvements in all
functional subsystems besides data transmission gateways, including
memory blocks. However, electronic RAM has proven
incapable of keeping pace with current processing speeds.
Limited memory bandwidth and long access times can degrade
overall system performance [5], forming a major bottleneck
in system’s performance that is commonly referred to as the
“Memory Wall” [5].