Although a detailed analysis of the pros and cons of disabling cache lines is outside the scope of this paper, our analysis shows that the probability of failures in robust cells is extremely low at the voltages we consider. For example, we find that 99.9% of the L3 caches will suffer failures in less than 1% of all lines at low voltage (Section 4). It's worth noting, however, that despite the minimal loss of capacity in the average set, specific sets may suffer significant capacity loss. These sets may cause performance outliers when running workloads that exercise them heavily. Due to this performance variability some designs