The test graphs were incorporated into a VHDL testbench and the functionality of the design was verified using the ModelSim simulator. Also, the design was verified in actual hardware using an FPGA development board by configuring the FPGA with a 16-node SPCU. For the sake of convenience, a circuit emulating the host’s behaviour was also implemented on the FPGA itself. The shortest paths computed by the FPGA-based SPCU were verified to be accurate.