Know the Operation
The RAM memory system shown in Figure 11-42 will be used in our examples. As
we emphasized in earlier discussions, successful troubleshooting of relatively
complex circuit or system begins with a thorough knowledge of its operation. Before we can discuss the testing of this RAM system, we should first analyze it carefully so that we fully understand its operation.
The total capacity is 4K x 8 and is made up of four 1K x 8 RAM modules. A module may be just a single IC, or it may consist of several ICs(e.g two 1K chips). Each module is connected to the CPU through the address and data busus and through the R/W control line. The modules have common I/O data lines. During a read operation these lines become data output lines through which the selected module places its data on the bus for the CPU to read. During a write operation, these lines act as input lines for the memory to accept CPU-generated data from the data bus for writing into the selected location.
The 74ALS138 decoder and the four-input OR gate combine to decode the high-order address lines to generate the chip select signals kO, k1, K2, and k3 These signals enable a specific RAM module for a read or a write operation. The IN VERTER is used to invert the CPU-generated Enable signal(E) so that the decoder is enabled only while E is HIGH. The E pulse occurs only ater allowing enough time for the address lines to stabilize following the application of a new address on the address bus, E will be LOW while the address and R/W lines are changing: this prevents the
occurrence of decoder output glitches that could erroneously activate a memory chip and possibly cause invalid data to be stored.
Each RAM module has its address inputs connected to the CPU address hus lines Ao through A9. The high-order address lines A10 through A15 select one of the RAM modules. The selected module decodes address lines A0 through A9 to find the word location that is being addressed. The following examples will show how to determine the addresses that correspond to each module.