Unlike earlier low density Shadow
RAM approaches, small cell size is achieved here by utilizing a vertically integrated IT-IC DRAM element
merged with a highly compact, vertically integrated, triple-level poly-silicon floating gate structure. Non-volatile operations on the floating gate stack are performed by Fowler-Nordheim electron injection through both a tunnel oxide, and through a first level to third level poly-silicon sidewall which has proven successful in earlier EPROMs.