Even with careful methodological guidance, it is still possible to introduce unintended and undesirable behaviors into function specifications,
high level architecture models or function-architecture
mappings. Foremost among these are deadlock, livelock and starvation.
Being semantic in nature, their complete and precise characterization
requires formal analysis or verification, which can only be
done at a high level of abstraction due to the state space explosion
problem. In this work, We look for a practical solution to deal with
these design problems in realistic and complex system designs. A
simulation based analysis methodology is proposed for the detection
and elimination of these “semantic errors”. Designers are responsible
for coming up with simulation vectors and scenarios that
are important and may lead to undesirable behaviors such as a deadlock.
Our approach automatically analyzes the simulation status and
reports deadlocks once they occur.