Synchronous digital systems have a master clock generator that supplies a continuorx train of
clock pulses. The clock pulses are applied to all flip-flops and registers in the systern The master
clock acts like a pump that supplies a constant beat to all parts of the system. A separate control
signal must be used to decide which specific clock pulse will have an effect on aparticular
register. The transfer of new information into a register is referred to as loading&reregister. If
all the bits of the register are loaded simultaneously with a common clock pulse, we say that
the loading is done in parallel. A clock edge applied to the C inpurs of the registcr of Eg. 6-1
will load all four inputs in parallel. In this configuration, the clock must be intribitedfrom the
circuit if the content of the register must be left unchanged. The clock can be inhibited from
A 4-bit register with a load control input that is directed through gates and into the D inputs
of the flip-flops is shown inFig. 6-2. The load input to the register determines the action to be
taken with each clock pulse. When the load input is 1, the data in the four inputs are transferred
into the register with the next positive edge of the clock. When the load input is 0, the
outputs of the flip-flops are connected to their respective inputs. The feedback connection from
output to input is necessary because the D flip.flsp does not have a "no change" condition. With
each clock edge, the D input determines the next state of the register. To leave the output
unchanged, it is necessary to make the D input equal to the present value ofthe output.