The next step is generation of clock tree. It is termed as Clock Tree Synthesis (CTS). How the clock is distributed in a design is one of the most limiting factors in order to achieve high frequency circuits. The clock signal has to get all the clocked components at the same time in order to achieve a correct operation, and the more the frequency is increased, the more clock inaccuracy we have. The generated clock tree is highlighted in white lines as shown in Figure 8. The density of the design after clock tree synthesis is 25.813%.