Also, when reducing power consumption, operation error caused by either disturbance noise or internally generated noise resulting when the power supply voltage is decreased becomes a major reliability concern. The CMOS device latchup phenomenon is a representative example of this. Since the well area electrically isolates bulk CMOS devices from the substrate, a parasitic thyrister is inevitably constructed between the power supply and GND pins. Latch-up is the phenomenon in which this parasitic thyrister is activated by well/substrate current resulting from either a disturbance surge or internal transistor operation. As a result, the system will either malfunction or shut down. (See Figure 8.) This phenomenon is more likely to occur when the device integration is improved and when the device temperature increases. Placing fixed substrate layers and independent well drain holes between all devices with different polarities generally prevents occurrences of this phenomenon. However, these measures cannot prevent the area that the devices occupy from increasing. In the case of SOI-CMOS devices, each element is completely isolated by BOX oxide film and LOCOS oxide film, so no parasitic thyristers are formed and the latch-up phenomenon does not occur. It is not necessary to place fixed layers and drain layers. Also, improved integration and improved hightemperature operation performance can be expected.