The larger a cache is, the less benefit it tends to see from associativity, since there is a lower probability that any two addresses will map onto the same space in the cache. Finally, successive increases in associativity have diminishing returns. Going from a direct-mapped cache to two-way set-associative usually causes significant reductions in the miss rate. Increasing to four-way set-associative (associativity is usually a power of 2 to simplify the hardware, but other associativities are possible) has a less significant effect, and increasing beyond that tends to have very little effect, except for extremely small caches. For this reason two-way and four-way set- associative caches are most common in current microprocessors.