Note that the same treatment can be extended for a parallel RLC load. The double-tuned matching network then consists of two stages. The first stage sets up the impedance locus for the second stage by meeting a specific set of constraints, while the second stage of the matching network brings the impedance locus below the given VSWR level. This paper is concerned primarily with the design of the second stage of the double-tuned matching network, specifically for cases where the first stage does not meet all the constraints.