Microelectronics has been the most important driving force for almost all kinds of technology evolutions in the past four decades.1,2 The size of the metal-oxide-semiconductor (MOS) transistor, which underpins Si microelectronics, has been reduced to a factor of 1,000 (Fig. 1). Silicon MOS technology has now been developed into two extremes: as fine as nanometer size in the device structures and as large as gigascale in terms of number of transistors in a chip. The downsizing rate of the MOS component is really impressive; now, we have sub-100 nm gate length transistors in production and R&D for 5 nm gate length devices is also on the way.2 The technology is expected to continue its historical advancing rate with Moore’s law for a couple of decades although there are many constraints ahead (Fig.2).3 [Editorial Note: This topic has been addressed recently in these magazine pages, see Interface, Spring 2005.] With this trend, the silicon gate oxide will be scaled down to its physical limit4 to keep the proper functioning of the transistors in the sub-10 nm technology node.
Microelectronics has been the most important driving force for almost all kinds of technology evolutions in the past four decades.1,2 The size of the metal-oxide-semiconductor (MOS) transistor, which underpins Si microelectronics, has been reduced to a factor of 1,000 (Fig. 1). Silicon MOS technology has now been developed into two extremes: as fine as nanometer size in the device structures and as large as gigascale in terms of number of transistors in a chip. The downsizing rate of the MOS component is really impressive; now, we have sub-100 nm gate length transistors in production and R&D for 5 nm gate length devices is also on the way.2 The technology is expected to continue its historical advancing rate with Moore’s law for a couple of decades although there are many constraints ahead (Fig.2).3 [Editorial Note: This topic has been addressed recently in these magazine pages, see Interface, Spring 2005.] With this trend, the silicon gate oxide will be scaled down to its physical limit4 to keep the proper functioning of the transistors in the sub-10 nm technology node.
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