In this brief, a novel, low-complexity, high-speed, and
resource-efficient address generator for the channel deinterleaver
used in the WiMAX transreceiver eliminating the requirement
of floor function is proposed. Very few works related
to hardware implementation of the interleaver/deinterleaver
used in a WiMAX system is available in the literature. The
work in [3] demonstrates the grouping of incoming data streams
into the block to reduce the frequency of memory access
in a deinterleaver using a conventional look-up table (LUT)-
based CMOS address generator for WiMAX. Khater et al.
[4] has described a hardware description language (VHDL)-