To address increasing energy/power consumption in
DRAMs, recent studies investigated new DRAM system
and chip organizations. They try to reduce DRAM energy
consumption by reorganizing conventional DRAM system
or chips into several smaller structures [2, 6, 25, 28]. However,
this approach increases the complexity of DRAM organization
and error protection strategies due to its data layout
modification. Even comprehensive hardware and software
supports are required to take full advantage of the
approach [26]. In contrast, we take advantage of inherent
fine-grained organization of the conventional DRAM system
non-intrusively with low overheads