III. MEMORY HIERARCHY, CACHES, AND CROSSBAR
Niagara2 has four memory controllers on chip, each controlling
two FBDIMM channels. They are clocked by the DR
(DRAM) clock, which nominally runs at 400 MHz corresponding
to the FBDIMM SerDes link rate of 4.8 Gb/s. Up
to eight DIMMs can be connected to each channel. Every
transaction from each controller consists of 64 data bytes and
ECC. Read transactions take two DR clock cycles, while Write
transactions take four DR clock cycles. This yields a Read
bandwidth of 51.2 GB/s and a Write bandwidth of 25.6 GB/s.