This type of behavior is common throughout sequential systems.
Usually, all flip flops in the system are triggered by the same clock.
Often, the inputs to flip flops are a function of the contents of the flip
flops of the system, as was shown in the global view of a sequential system
at the beginning of this chapter.
Before going on to look at other types of flip flops, we will examine
the behavior of flip flops with static (asynchronous) clear* and preset
inputs. Any type of flip flop may have one or both of these available. A D
flip flop with active low (the most common arrangement) clear and preset
inputs is shown in Figure 6.14.
The version on the left uses overbars
for the complement (the most common notation in the integrated circuit
literature); we will continue to use primes, as on the right, where the
behavior of the flip flop is described by the truth table of Table 6.4. The
clear and preset inputs act immediately (except for circuit delay) and
override the clock, that is, they force the output to 0 and 1, respectively.
Only when both of these static inputs are 1, does the flip flop behave as
before, with the clock transition and the D input determining the behavior.
A timing example is shown in Figure 6.15.
The clear input becomes
active near the beginning of the time shown, forcing q to 0. As long as
that input remains 0, the clock and D are ignored; thus, nothing changes
at the first trailing edge of the clock that is shown. Once the clear returns
to 1, then the clock and D take over; but they have no effect until the next
trailing edge of the clock.
The D input determines the behavior of the flip
flop at the next four trailing edges. When the preset input goes to 0, the
flip flop output goes to 1. When the preset input goes back to 1, the clock
and D once again take over.