Abstract—In designing high efficiency, large step down buck
converters, the power semiconductors contribute a significant
loss mechanism through switching losses. Minimizing these losses
can be achieved by running at lower frequencies, decreasing the
actual switching time, or performing soft switching. However,
soft switching converters introduce extra components, which can
impact reliability, cost, and size of the final converters. Therefore,
extremely rapid hard switching is preferable to soft switching
converters. This paper proposes a new layout technique for low
parasitic inductance paths using commercially standard PCB
specifications for very fast switching speeds of GaN power devices
in flip-chip packages resulting in a highly efficient (>94%) hard
switching 12-1 V synchronous buck converter. The proposed
technique is experimentally verified at output loads from 4 -
20 A and achieves less than 5 ns switching times.