For example, a chemical mechanical polishing (CMP)
research group in a school of mechanical engineering
wants to study its polishing technique on dielectric and/or
metal, with line/spacing of patterns around 1 m, in wafer
scale. This project does not require the knowledge of all
of CMOS processing. Therefore, the training for this group
118 IEEE TRANSACTIONS ON EDUCATION, VOL. 47, NO. 1, FEBRUARY 2004
focused on wet/dry oxidation, optical lithography, PECVD
nitride/oxide growth, metal sputtering/electroplating, and RIE
dielectrics/metals etch. The training of the combination of the
individual processing modules for the group helped them to
understand the real semiconductor processing procedures and
offered them an opportunity to apply their CMP technique,
which was designed for unpatterned wafer polishing, to a study
on the dishing and erosion of copper vias on a patterned silicon
wafer. Dr. C. Zhou of Lam Research, who was a Postdoctoral
Fellow in charge of the CMP project while in Georgia Tech
from 2000 and 2002, said, “The MiRC training program provided
me with better technology for advanced CMP research
and helped me raise my research goals. I am still benefiting
from what I have learned from the MiRC training program
even though I am now with a major semiconductor equipment
manufacturer. I am glad I participated in the MiRC training
program. It really prepared me well for what I need to do daily
here.”