The main drawback to the bus organization is performance. All memory references
pass through the common bus.Thus, the bus cycle time limits the speed of the
system.To improve performance, it is desirable to equip each processor with a cache
memory. This should reduce the number of bus accesses dramatically. Typically,
workstation and PC SMPs have two levels of cache, with the L1 cache internal
(same chip as the processor) and the L2 cache either internal or external. Some
processors now employ a L3 cache as well.
each processor remain the same as in a single-processor system.
• Flexibility: It is generally easy to expand the system by attaching more processors
to the bus.
• Reliability: The bus is essentially a passive medium, and the failure of any
attached device should not cause failure of the whole system.