The test chip of the 3DG IP and the EDPME is fabricated using
TSMC 0.18Ǵm 1P6M CMOS process (See Fig. 5). Its size is
15.68mm2
and it runs at 139MHz. Table II gives a detailed specification. In conclusion, the EDPME can be facilitated on-chip bus integration, real time profiling, debugging and performance measurement/tuning with up to 98% trace compression ratio.