of that of the decoder in [13]. Alt

of that of the decoder in [13]. Although keeping all messages
in a vector leads to simpler vector addition and subtraction,
it also results in larger memory requirement, which dominates
the area of NB-LDPC decoders. In addition, the CNU
architecture in [12] has much longer latency than our design.
Therefore, the decoder architecture employing the CNU in [12]
is not further compared.
With less than half of the area, the proposed decoder can run
at the same speed as the previous best design. The area saving
mainly comes from memory reduction, which is achieved by not
only the novel sorting and path construction based check node
processing, but also the innovative idea of storing the c-to-v
messages in a “compressed” manner. In the decoder architecture
in [13], eight copies of RAM A are employed. They account
for more than 75% of the overall decoder area. One RAM
A is used for storing the channel information as in the proposed
decoder. Two of them are used to store intermediate results in
the forward-backward check node processing, and three copies
are adopted for recording the c-to-v messages. In addition, another
two RAM A blocks are used to hold the v-to-c input messages
to the CNU to be used for computing the a posteriori mes